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Analysis of Trapped Charge Migration at 3D NAND Flash Memory with Multi Level Operation : 멀티 레벨로 동작하는 3차원 구조 낸드 플레쉬 메모리의 포획 전하 이동에 관한 연구

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Authors

박상구

Advisor
박병국
Major
공과대학 전기·정보공학부
Issue Date
2017-02
Publisher
서울대학교 대학원
Keywords
3D NAND flashmulti-level operationtrapped charge migrationretentioncell Vth
Description
학위논문 (석사)-- 서울대학교 대학원 : 전기·정보공학부, 2017. 2. 박병국.
Abstract
3D structure improves capacity and performance of NAND flash memory, however, new structure of device caused unexpected problems especially in device reliability. One of the most critical reliability issue of NAND flash memory is data retention. At the gate stack type 3D NAND structure, NAND cells sharing storage layer and trapped charges in target cell (TC) storage layer are able to migrate to the both side cells (SC). Migration of trapped charge critically affects reliability characteristic of NAND flash memory. Most researches focus have been on decrease of threshold voltage (Vth) of TC during data retention test. While with multi or higher level operation, both SCs Vth could be set as much higher than TC Vth. In this case, trapped charges in storage layer of SCs migrate to the TC region and the migration could be dominant mechanism of data retention at the initial state of device operation. To analyze trapped charge migration at the 3D NAND flash cells, we conducted retention simulation. For the simulation of electron migration from SC to TC region, SC Vth is set up much higher than TC Vth and the charge centroid is controlled to locate in the storage layer. Using the trapped charge contour data at each time step of retention simulate, we analyze the effect of trapped charge migration on the change of the TC Vth. We confirm the results of simulation by retention tests at the 3D NAND flash memory device. To reflect various operation conditions of multi or higher level operation, we set up five test patterns. Difference between TC and SC Vth affects trapped charge migration and change of TC Vth during retention test. Tunneling of charges is changed by TC Vth level but minimized at the retention tests to analyze the effect of migration dominantly. Finally, we conducted temperature split retention test at the test cases that TC Vth increases and decreases. Because the trapped charge migration and tunneling are affected by bake temperature, change of TC Vth should be analyzed at various temperature condition for the memory device reliability.
Language
English
URI
https://hdl.handle.net/10371/122866
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