Three dimensional simulation of retention characteristics of Charge Trap (CT) NAND Flash memory

Abstract

To investigate the retention characteristics of the CT (Charge Trap) Flash memory, the simulation study with various NAND Flash structures has been conducted using the three dimensional self-consistent simulator [1], which is the 3D simulator developed in house, considering the vertical and lateral charge transport in the conduction band of the nitride layer. All the simulations are based on the SANOS (Si /Al2O3/ Si3N4/ SiO2/Si) device with the SA-STI (Self-Aligned Shallow Trench Isolation) structure. Prior to retention simulations, the programming simulation has been conducted under the temperature 300K by enforcing the 18V to the gate electrode to extract the initial charge density distribution of the retention situation. The programming is stopped when the threshold voltage shift is 4V, and the charge distribution is settled as the initial charge density distribution of the retention simulation. First of all, to ascertain the dependency on the extended nitride length over the gate region, several structures (0nm, 15nm, 30nm, 150nm) are simulated. Since the emitted electrons cannot transport over the nitride region, the extended nitride length decides the saturation point of the charge loss. Because NAND Flash memory has an array structure, the charge transport to the extended nitride region could affect the neighbor cells. To demonstrate this phenomenon, two programmed patterns (check-board pattern and solid pattern) are simulated. In the check-board pattern, the threshold voltage of the eased cell has increased. The charge loss speed of the programmed cell, in the solid pattern, has decreased until the programmed electrons spread and stop at the lateral edge. The retention cycle (Program- Retention-Erase) behavior has been also simulated. The charges which have been trapped in the extended region in the previous retention-term disturb the additional transport to the extended nitride region in the next retention mode. This causes a change in the slope of the retention curve. The activation energy of the CT Flash memory has been also studied by simulating the various tunneling oxide thickness, considering charge transport along the vertical and lateral directions. And then, the various forms of the Arrhenius plot have been modeled by separating the temperature ranges into three regions. At high temperature (Region-1), the charge loss is mainly affected by thermal emission and electron transport, so that the activation energy is same as the the tunneling free case. The temperature region showing reduced activation energy is called Region-2. Since the impact of the tunneling current become larger, the Arrhenius plot under high temperature region is depressed. In the low temperature (Region-3), thermal energy is needed to move the electrons to the tunneling interface or outside of the gate region until the charge loss reaches the criterion. Thus, the activation slope is increased up to that of the device with thick tunneling oxide. Consequently, in this thesis, the dependency of the extended nitride length, the programmed pattern and the retention cycle is confirmed as an important factor in analyzing the retention characteristics of the SANOS cells. Various forms of the Arrhenius plot are understood by the charge transport model.