S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Theses (Master's Degree_전기·정보공학부)
Investigation of Three Dimensional NAND Flash Memory Based on Gate STacked ARray (GSTAR) : Gate 적층 구조를 가지는 3차원 NAND Flash Memory의 제안 및 검증
- 공과대학 전기·컴퓨터공학부
- Issue Date
- 서울대학교 대학원
- 학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 박병국.
- Weve developed a Gate STacked ARray (GSTAR) structure as a three-dimensional memory, which extremely reduces the chip costs by vertically stacking memory arrays with easier process steps. The proposed device is a gate stack type structure having U-shaped channel to achieve high memory density without shrinking cell channel length. The GSTAR, by using an ultra-thin body structure, can reduce the off-current level, and planar cell type of GSTAR assures insensitivity to process variables such as etch-slope. The performance of designed structure is described and the optimization of device parameter is performed by using TCAD simulation. To increase device performance and ease of fabrication, the modified fabrication method to reduce the spacing between gates is also introduced.