Analysis of nano-scale PMOSFET degradation under GIDL stress conditions

Abstract

The device degradation under gate-induced drain leakage (GIDL) mode stress is studied in nano-scale p-MOSFET for DRAM peripheral circuit. In order to discuss the degradation mechanism in p-MOSFET, the GIDL current and the other electrical parameters of target p-MOSFET are measured before and after high bias stress with different stress times. 2D TCAD simulation was performed using SENTAURUSTM to know the internal physics of the p-MOSFET fabricated on the silicon substrate using the conventional CMOS process. With an intensive simulation, the gate or drain bias dependencies of the drain current before and after GIDL stresses of target device are fitted to the measurement results. Because band-to-band tunneling (BTBT) and trap-assisted-tunneling (TAT) are the main mechanisms for generating GIDL currents, the appropriate physical model was selected in the simulation set and modified for the tunneling mechanism. According to the stress time, the changes of GIDL current and the on-state drain current before and after stress can be divided into two stages. The degradation mechanisms under GIDL stress are analyzed by considering TAT, BTBT, channel length modulation (CLM), and parasitic resistance degradation. It is found that the generation of interface states and the trapping of different types charges cause the degradation of p-MOSFET under GIDL stress. The simulation shows clearly the relationship between charge density and stress time, interface trap density and stress time.