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Design Methodologies using Multi-bit Flip-flops for Low Power : 다중-비트 플립-플롭을 활용한 저전력 설계 방법론

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dc.contributor.advisor김태환-
dc.contributor.author문형석-
dc.date.accessioned2018-05-28T16:18:32Z-
dc.date.available2018-05-28T16:18:32Z-
dc.date.issued2018-02-
dc.identifier.other000000149989-
dc.identifier.urihttps://hdl.handle.net/10371/140652-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2018. 2. 김태환.-
dc.description.abstractMerging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this dissertation, a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF) is introduced. The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart, providing no need to set aside white space (i.e., no relocation) and relaxed timing check requirement. Utilizing LC-MBFFs, an multi-bit flip-flop allocation algorithm considering the routability and the clock tree, which fully explores the diverse allocation of LC-MBFF structures is also proposed to maximally reduce clock power consumption.
Additionally, the proposed algorithm is extended to efficiently support the multi-bit flip-flop allocation for circuits with clock polarity assignment. Clock polarity assignment is a technique to mitigate power/ground noise by assigning different clock polarities to clock buffers.
Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that the proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power consumed in the flip-flops by 8.51% on average while the best known multi-bit flip-flop allocation algorithm reduces by 3.55% on average. Also it is shown that the extended noise-aware algorithm is effective in power/ground noise mitigation.
In summary, this dissertation presents a new style of multi-bit flip-flop and allocation algorithms, to save clock power consumption and to mitigate power/ground noise.
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dc.description.tableofcontents1 INTRODUCTION 1
1.1 Multi-bit Flip-flop 1
1.2 Related Works 4
1.3 Contributions of This Dissertation 12
2 LOOSELY COUPLED MULTI-BIT FLIP-FLOP 14
2.1 Illustration of limited applicability of MBFF allocation 14
2.2 Structure of LC-MBFF 18
2.3 Feasibility Analyses of LC-MBFF 21
2.3.1 Timing 22
2.3.2 Power Consumption 41
2.3.3 Routability 48
3 ALGORITHM FOR LC-MBFF ALLOCATION 49
3.1 Design Constraints and Flow 49
3.2 The LC-MBFF allocation algorithm 50
4 APPLICATION TO CLOCK POLARITY ASSIGNED CIRCUITS 54
4.1 Clock Polarity Assignment 54
4.2 LC-MBFF with Different Clock Polarities 57
4.3 Modification of LC-MBFF Allocation Algorithm 59
5 EXPERIMENTAL RESULTS 61
5.1 Experimental Setup 61
5.1.1 The Maximum Merging Distance 62
5.1.2 The Clock Polarity Assignment 62
5.2 LC-MBFF Allocation 64
5.3 Noise-aware LC-MBFF Allocation 71
6 CONCLUSIONS 73
Appendices 75
A Maximum Weighted Matching for 2-bit LC-MBFF Allocation 76
B Maximum Weighted Independent Set for LC-MBFF Allocation 80
Abstract (In Korean) 87
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dc.formatapplication/pdf-
dc.format.extent7447037 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectflip-flop-
dc.subjectmulti-bit-
dc.subjectpower-
dc.subjectclock polarity assignment-
dc.subjectpower/ground noise-
dc.subject.ddc621.3-
dc.titleDesign Methodologies using Multi-bit Flip-flops for Low Power-
dc.title.alternative다중-비트 플립-플롭을 활용한 저전력 설계 방법론-
dc.typeThesis-
dc.contributor.AlternativeAuthorHyoungseok Moon-
dc.description.degreeDoctor-
dc.contributor.affiliation공과대학 전기·정보공학부-
dc.date.awarded2018-02-
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