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Modeling of gate induced drain leakage current in DRAM cell transistor : DRAM Cell 소자에서의 게이트 유기 드레인 누설 전류 모델링
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- Authors
- Advisor
- 신형철
- Major
- 전기. 컴퓨터공학부
- Issue Date
- 2011-08
- Publisher
- 서울대학교 대학원
- Keywords
- 게이트 유기 누설 전류 ; 반도체 소자 모델링 ; SRCAT ; Gate induced drain leakage (GIDL) ; Semiconductor device modeling ; Sphere-shaped recessed channel array transistor (SRCAT) ; Field-effect factor ; Trap assisted tunneling (TAT) ; Poole-Frenkel effect (PFE).
- Description
- 학위논문 (석사)-- 서울대학교 대학원 : 전기. 컴퓨터공학부, 2011.8. 신형철.
- Language
- eng
- URI
- https://hdl.handle.net/10371/159664
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000031711
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