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Design of Wide-Range Clock and Data Recovery with Multi-Phase Oversampling Frequency Detection
다중 위상 오버샘플링 주파수 검출 방식을 이용한 광대역 클럭 및 데이터 복원회로 설계

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dc.contributor.advisor정덕균-
dc.contributor.author박관서-
dc.date.accessioned2019-10-21T02:15:02Z-
dc.date.available2019-10-21T02:15:02Z-
dc.date.issued2019-08-
dc.identifier.other000000157673-
dc.identifier.urihttp://hdl.handle.net/10371/161983-
dc.identifier.urihttp://dcollection.snu.ac.kr/common/orgView/000000157673ko_KR
dc.description학위논문(박사)--서울대학교 대학원 :공과대학 전기·정보공학부,2019. 8. 정덕균.-
dc.description.abstractIn this thesis, design techniques of a wide-range clock and data recovery (CDR) without a reference clock are proposed. For the referenceless operation, a frequency acquisition scheme using multi-phase oversampling is utilized. The analysis of the representative performances such as capture range and frequency acquisition time is provided and demonstrated by the measurement results. Furthermore, to achieve an unlimited frequency detection capability, an advanced referenceless CDR with a digital implementation is proposed.
At first, a single-loop referenceless CDR with a compact frequency acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the NRZ bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. The UP/DN output signals from the BBPFD are connected directly to the loop filter, thereby reducing the acquisition time without any loss of cycles. When frequency lock is reached, the BBPFD is degenerated into the conventional bang-bang phase detector (BBPD). The effect of sampling phase mismatch is analyzed and the capture range is calculated. In addition, the frequency acquisition time is analytically derived and verified by simulation. The proposed CDR has been implemented in a 65 nm CMOS process and occupies an active area of 0.047 mm2. The measured capture range is 6.7-to-11.2 Gb/s and the frequency acquisition time is less than 2.19 μs. The proposed CDR achieves error-free operation (BER < 10-12) for PRBS31 pattern and consumes 22.5 mW at 10 Gb/s.
Advanced from the previous version, a referenceless digital CDR with an unlimited frequency detection capability is proposed. Based on the detailed capture-range analysis of the multi-phase oversampling scheme, a frequency detector with additional logic gates is proposed and its frequency detection curve shows an unlimited capability. Unlike the prior works, the proposed CDR achieves frequency acquisition regardless of the initial condition and its capture range is determined only by the operating range of the oscillator. The CDR fabricated in 65 nm CMOS consumes 37.3 mW at 20 Gb/s and occupies an active area of 0.045 mm2. The measured capture range is from 4 Gb/s to 20 Gb/s and the worst-case acquisition time is 25 μs with a PRBS31 pattern.
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dc.description.abstract본 논문에서는 다중 위상 오버샘플링 주파수 검출 방식 (multi-phase oversampling frequency detection)을 이용하여 기준 클락이 없는 시스템 (referenceless system)에서 사용될 클럭 및 데이터 복원회로 (clock and data recovery)를 설계하는 방법을 제안한다. 기존 방식들과 비교하여 포획범위, 파워, 추적시간 세가지 성능에서 이점을 가지는 새로운 방식을 제안한다. 제안한 뱅뱅 위상-주파수 검출기 (bang-bang phase-frequency detector)는 다중 위상 클럭과 데이터와의 상대적인 위상 이동방향을 감지하여 주파수 차이를 검출한다. 제안하는 방식의 포획범위, 추적시간에 대한 이론적인 분석을 통해 나온 결과를 시뮬레이션과 측정을 통해 검증하였다. 65nm CMOS 공정을 이용하여 만들어진 칩은 10 Gb/s에서 22.5 mW의 파워를 소모하고 0.047 mm2의 면적을 차지한다. PRBS31 패턴을 이용하여 측정되었고 포획범위는 6.7 Gb/s에서 11.2 Gb/s까지이고 추적시간은 2.19 μs 보다 작다. 제안하는 클럭 및 데이터 복원회로는 비트에러율 10-12 이하 기준에서 문제없는 동작을 보여주었다.
앞선 버전에서 발전하여, 제한 없는 주파수 검출 능력을 가지는 클럭 및 데이터 복원회로를 제안한다. 동일하게 다중 위상 오버샘플링 주파수 검출 방식을 기반으로 하였고 추가적인 기능을 통해 포획범위 제한을 없애게 되었다. 또한, 초기 주파수 조건에 상관없이 주파수 검출이 가능하다. 65nm CMOS 공정을 이용하여 만들어진 칩은 20 Gb/s에서 37.3 mW의 파워를 소모하고 0.045 mm2의 면적을 차지한다. PRBS31 패턴을 이용하여 측정되었고 포획범위는 4 Gb/s에서 20 Gb/s까지이고 이는 단지 발진기의 동작범위에 의해 제한되었다. 그 범위에서의 추적시간은 25 μs보다 작다.
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dc.description.tableofcontentsChapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Chapter 2 Backgrounds 5
2.1 Clocking in Serial Link 5
2.2 Clock and Data Recovery 11
2.1.1 General Considerations 11
2.1.2 CDR Architectures 13
2.1.3 Types of Phase Detector 20
2.2 Referenceless CDR 24
2.2.1 Overview 24
2.2.2 Typical Frequency Detector 26
2.2.3 Frequency Acquisition Techniques 31
Chapter 3 Referenceless CDR with Multi-Phase Oversampling PFD 35
3.1 Overview 35
3.2 Proposed Frequency Acquisition 37
3.2.1 Operation of BBPD 37
3.2.2 Proposed Bang-Bang Phase-Frequency Detector 40
3.2.3 Analysis of Capture Range 48
3.2.4 Effect of Phase Mismatch 51
3.2.5 Frequency Acquisition Time 53
3.3 Circuit Implementation 59
3.3.1 Referenceless CDR Architecture 59
3.3.2 Ring VCO and BBPD 60
3.3.3 Charge Pump 63
3.4 Measurement Results 67
Chapter 4 Digital CDR with Unlimited Frequency Detection Capability 77
4.1 Overview 77
4.2 Multi-Phase Oversampling FD 80
4.2.1 Operation Principle 82
4.2.2 Effect of Frequency Offset on LAG/LEAD Regions 83
4.2.3 Capture-Range Limitation of Multi-Phase Oversampling FD 85
4.3 Proposed Frequency Detector 90
4.3.1 Capture-Range Extension 90
4.3.2 Frequency Detector with Unlimited Frequency Detection Capability 92
4.4 Circuit Implementation 97
4.4.1 Implementation of Digital CDR 97
4.4.2 Digitally-Controlled Oscillator 99
4.4.3 Frequency Lock Detector 100
4.5 Measurement Results 101
Chapter 5 Conclusion 110
Bibliography 112
초 록 123
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dc.language.isoeng-
dc.publisher서울대학교 대학원-
dc.subjectacquisition time-
dc.subjectbang-bang phase detector (BBPD)-
dc.subjectbang-bang phase-frequency detector (BBPFD)-
dc.subjectclock and data recovery (CDR)-
dc.subjectfrequency acquisition-
dc.subjectlow power-
dc.subjectmulti-phase oversampling-
dc.subjectphase-locked loop (PLL)-
dc.subjectreferenceless-
dc.subjectsingle loop-
dc.subjectunlimited frequency detection-
dc.subject.ddc621.3-
dc.titleDesign of Wide-Range Clock and Data Recovery with Multi-Phase Oversampling Frequency Detection-
dc.title.alternative다중 위상 오버샘플링 주파수 검출 방식을 이용한 광대역 클럭 및 데이터 복원회로 설계-
dc.typeThesis-
dc.typeDissertation-
dc.contributor.AlternativeAuthorKwanseo Park-
dc.contributor.department공과대학 전기·정보공학부-
dc.description.degreeDoctor-
dc.date.awarded2019-08-
dc.contributor.major집적시스템설계-
dc.identifier.uciI804:11032-000000157673-
dc.identifier.holdings000000000040▲000000000041▲000000157673▲-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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