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Self-Heating and Electrothermal Properties of Sub-5-nm 3-D Transistors : 5nm 이하 3D Transistors의 Self-Heating 및 전열특성분석 연구

DC Field Value Language
dc.contributor.advisor신형철-
dc.contributor.author명일호-
dc.date.accessioned2022-04-20T07:51:55Z-
dc.date.available2022-04-20T07:51:55Z-
dc.date.issued2021-
dc.identifier.other000000166800-
dc.identifier.urihttps://hdl.handle.net/10371/178950-
dc.identifier.urihttps://dcollection.snu.ac.kr/common/orgView/000000166800ko_KR
dc.description학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2021.8. 신형철.-
dc.description.abstractIn this thesis, Self-Heating Effect (SHE) is investigated using TCAD simulations in various Sub-10-nm node Field Effect Transistor (FET). As the node decreases, logic devices have evolved into 3D MOSFET structures from Fin-FET to Nanosheet-FET. In the case of 3D MOSFET, there are thermal reliability issues due to the following reasons: ⅰ) The power density of the channel is high, ⅱ) The channel structure surrounded by SiO2, ⅲ) The overall low thermal conductivity characteristics due to scaling down. Many papers introduce the analysis and prediction of temperature rise by SHE in the device, but there are no papers presenting the content of mitigation of temperature rise. Therefore, we have studied the methods of decreasing the maximum lattice temperature (TL,max) such as shallow trench isolation (STI) composition engineering in Fin-FET, thermal analysis according to DC/AC/duty cycle in nanowire-FET, and active region ( e.g., gate metal thickness, channel width, channel number etc..) optimization in nanosheet-FET. In addition, lifetime affected by hot carrier injection (HCI) / bias-temperature instability (BTI) is also analyzed according to various thermal relaxation methods presented.-
dc.description.abstract이 논문에서는 다양한 Sub-10nm 노드 전계 효과 트랜지스터 (FET)에서 TCAD 시뮬레이션을 사용하여 자체 발열 효과 (SHE)를 조사합니다. 노드가 감소함에 따라 논리 장치는 Fin-FET에서 Nanosheet-FET로 3D MOSFET 구조로 진화했습니다. 3D MOSFET의 경우 ⅰ) 채널의 전력 밀도가 높음, ⅱ) SiO2로 둘러싸인 채널 구조, ⅲ) 축소로 인해 전체적으로 낮은 열전도 특성 등 다음과 같은 이유로 열 신뢰성 문제가 있습니다. 한편, 많은 논문이 device에서 SHE에 의한 온도 상승의 분석 및 예측을 소개하지만 온도 상승 완화의 내용을 제시하는 논문은 거의 없습니다. 따라서 Fin-FET의 STI (Shallow Trench Isolation) 구성 공학, nanowire-FET의 DC / AC / 듀티 사이클에 따른 열 분석, nanosheet-FET에서 소자의 중요영역(예: 게이트 금속 두께, 채널 폭, 채널 번호 등)의 최적화를 통해서 최대 격자 온도 (TL,max)를 낮추는 방법등을 연구했습니다. 또한 더 나아가서 HCI (Hot Carrier Injection) / BTI (Bias-Temperature Instability)의 영향을 받는 수명도 제시된 다양한 열 완화 방법에 따라 분석하여 소자의 제작에 있어 열적 특성과 수명을 좋게 만드는 지표를 제시합니다 .-
dc.description.tableofcontentsChapter 1 Introduction 1
1.1. Development of Semconductor structure 1
1.2. Self-Heating Effect issues in semiconductor devices 3
Chapter 2 Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistor 7
2.1. Introduction 7
2.2. Device Structure and Simulation Condition 7
2.3. Results and Discussion 12
2.4. Summary 27
Chapter 3 Analysis of Self Heating Effect in DC/AC Mode in Multi-channel GAA-Field Effect Transistor 32
3.1. Introduction 32
3.2. Multi-Channel Nanowire FET and Back End Of Line 33
3.3. Work Flow and Calibration Process 35
3.4. More Detailed Thermal Simulation of Nanowire-FET 37
3.5. Performance Analysis by Number of Channels 38
3.6. DC Characteristic of SHE in Nanowire-FETs 40
3.7. AC Characteristics of SHE in Nanowire-FETs 43
3.8. Summary 51
Chapter 4 Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET 56
4.1. Introduction 56
4.2. Device Structure and Simulation Condition 57
4.3. Thermal characteristics by channel number and width 62
4.4. Thermal characteristics by inter layer-metal thickness (TM) 64
4.5. Life Time Prediction 65
4.6. Summary 67
Chapter 5 Study on Self Heating Effect and life time in Vertical-channel Field Effect Transistor 72
5.1. Introduction 72
5.2. Device Structure and Simulation Condition 72
5.3. Temperature and RTH according to channel width(TW) 76
5.4. Thermal properties according to air spacers and air gap 77
5.5. Ion boosting according to Channel numbers 81
5.6. Temperature imbalance of multi-channel VFETs 82
5.7. Mitigation of the channel temperature imbalance 86
5.8. Life time depending on various analysis conditions 88
5.9. Summary 89
Chapter 6 Conclusions 93
Appendix A. A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models 95
A.1. Introduction 95
A.2. Overall Schematic of the RF MOSFET Model 97
A.3. Verification of the DC Characteristics of the RF MOSFET Model 98
A.4. Verification of the MOSFET Model with Measured Y-parameters 100
A.5. Verification of the MOSFET Model with Measured Noise Parameters 101
A.6. Thermal Noise Extraction and Modeling (TNOIMOD = 0) 103
A.7. Verification of the Enhanced Model with Noise Parameters 112
A.8. Holistic Model (TNOIMOD = 1) 114
A.9. Evaluation the validity of the model for drain bias 115
A.10. Conclusion 117
Abstract in Korean 122
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dc.format.extentvi, 127-
dc.language.isoeng-
dc.publisher서울대학교 대학원-
dc.subjectself-heating-
dc.subjectlifetime-
dc.subjectlogic device-
dc.subjectnanosheetFET-
dc.subjectSelf-Heating Effect (SHE)-
dc.subjectNanoplate-FET-
dc.subjectNanowire-FET-
dc.subjectFinFET-
dc.subjectVertical-FET-
dc.subjectThermal resistance-
dc.subjectTemperature-
dc.subjectTime delay-
dc.subjectBias Temperature Instability (BTI)-
dc.subjectHot Carrier Injection (HCI)-
dc.subject자기 열 발생 효과-
dc.subject열 저항-
dc.subject온도-
dc.subject시간지연-
dc.subject전압-온도 불안정성 (BTI)-
dc.subject열 전자 효과 (HCI)-
dc.subject.ddc621.3-
dc.titleSelf-Heating and Electrothermal Properties of Sub-5-nm 3-D Transistors-
dc.title.alternative5nm 이하 3D Transistors의 Self-Heating 및 전열특성분석 연구-
dc.typeThesis-
dc.typeDissertation-
dc.contributor.AlternativeAuthorIlho Myeong-
dc.contributor.department공과대학 전기·컴퓨터공학부-
dc.description.degree박사-
dc.date.awarded2021-08-
dc.contributor.major반도체-
dc.identifier.uciI804:11032-000000166800-
dc.identifier.holdings000000000046▲000000000053▲000000166800▲-
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