A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

Abstract

As data transfer rates increase, clock frequencies used for high-speed data paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade the valid data sampling window. To reduce phase error, several multiphase correction schemes have been proposed [1]-[4]. The active poly-phase filter-based open-loop scheme exhibits a small RMS jitter contribution, but the remaining phase error after the error correction is considerably varied and large in its operating frequency range [1]. A distributed delay-locked loop (DLL) [2] offers the smallest RMS jitter, but the residual phase error is non-negligible as well due to the mismatch of error detection circuits in each calibration loop. The phase error corrector with a relaxation oscillator-based phase detector is also susceptible to the mismatch [3]. The digital DLL-based scheme adopts a shared digital feedback loop to eliminate the effect of mismatch [4]. However, it shows a larger RMS jitter contribution than the distributed DLL due to quantization noise and the increased clock path delay. Since the delay of in-phase clock is always fixed at the mid-point, overall set of codes of digitally-controlled delay lines (DCDLs) may not be at their optimum in terms of jitter. Because jitter and total delay of clock paths are increased more than necessary, it leads to degradation of the data eye. In this paper, an improved quadrature error corrector (QEC), the calibration of which starts from the minimum delay code over all DCDLs, is proposed along with an asynchronous and seamless-calibration on-off scheme for the reduction of power consumption in the operating state after calibration.