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A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS

Cited 8 time in Web of Science Cited 7 time in Scopus
Authors

Park, Kwanseo; Lee, Kwangho; Cho, Sung-Yong; Lee, Jinhyung; Hwang, Jeongho; Choo, Min-Seong; Jeong, Deog-Kyoon

Issue Date
2019-06
Publisher
IEEE
Citation
2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195
Abstract
This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme, The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 mu s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm(2)
URI
https://hdl.handle.net/10371/186750
DOI
https://doi.org/10.23919/VLSIC.2019.8778157
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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