Low-cost Technique for Measuring Clock Duty Cycle on FPGAs

Abstract

A circuit for on-chip measurement of duty cycle for unknown clock is demonstrated. The circuit consists of variable delay, counter and AND gate, and can be implemented on FPGA that has variable delay element without any external supporting circuit and occupies a very small portion of the FPGA. The major benefit over the previous measurement technology is that statistical analysis of the duty cycle of a large number of continuous clock cycles is possible through a single measurement.