A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter

Abstract

The low-power and small-area implementation of a multi-GS/s sub-ADC with a moderate ENOB (6-8b) is essential to reducing the silicon area of high-speed time-interleaved ADCs (Tl-ADCs). Flash ADCs are best suited for increasing sampling rates, but they require large area and power to achieve a higher resolution. Pipelined SAR ADCs can have high sampling rates and resolution simultaneously without increasing the area proportionally. However, they require multiple residue amplifiers (RAs) and calibration circuits between stages to maintain a constant interstagegain, which inevitably increases power and complexity [1]. Recently, timedomain (TD) ADCs began to emerge with their distinct merits of power/area scalability at submicron nodes. Multi-stage TD quantizers consisting of a voltage-to-time converter (VTC) and a TDC are popular for increasing the sampling rates and resolution, but linear VTCs [2] and RAs [3] still require large power. The left of Fig. 1 shows another TD ADC using a ring-VCO-based quantizer [4] that potentially can use minimal hardware resources. However, the inherent problem of a VCO-based quantizer, i.e., a nonlinear voltage-to-frequency gain (K_VCO) over the full range of the input voltage (V_S), mandates complex post-linearity calibration, and this requires increases in both area and power. Moreover, since the post calibration of K_VCO amplifies the quantization noise (O-noise) in regions where the original K_VCO is small, it also degrades the overall SNR, which results in the significant degradation of ENOB.