Publications
Detailed Information
A 0.016 mm<SUP>2</SUP> 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS
Cited 1 time in
Web of Science
Cited 2 time in Scopus
- Authors
- Issue Date
- 2019-08
- Citation
- IEEE Journal of Solid-State Circuits, Vol.54 No.8, pp.2186-2194
- ISSN
- 0018-9200
- Files in This Item:
- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.