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Boltzmann Switching MoS2 Metal–Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky–Mott Limit

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Authors

Kim, Yeon Ho; Jiang, Wei; Lee, Donghun; Moon, Donghoon; Choi, Hyun-Young; Shin, June-Chul; Jeong, Yeonsu; Kim, Jong Chan; Lee, Jaeho; Huh, Woong; Han, Chang Yong; So, Jae-Pil; Kim, Tae Soo; Kim, Seong Been; Koo, Hyun Cheol; Wang, Gunuk; Kang, Kibum; Park, Hong-Gyu; Jeong, Hu Young; Im, Seongil; Lee, Gwan-Hyoung; Low, Tony; Lee, Chul-Ho

Issue Date
Publisher
WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Citation
Advanced Materials, p. 2314274
Abstract
A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal–semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec−1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky–Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.
ISSN
0935-9648
URI
https://hdl.handle.net/10371/203509
DOI
https://doi.org/10.1002/adma.202314274
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  • College of Engineering
  • Department of Materials Science & Engineering
Research Area 2D materials, 2차원 물질, Smiconductor process, semiconductor devices, 반도체 공정, 반도체 소자

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