Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller

Abstract

In this work, we address the synthesis problem of two-phase bundled-data asynchronous pipeline controllers, in which the insertion of buffers is essential for guaranteeing the correct handshaking operation on every pipeline stage at the expense of considerable area increase. To lighten the pipeline controllers, we introduce a new logic synthesis concept called delay path sharing and reusing, by which we can significantly reduce the amount of the costly delay buffers. Precisely, first, we propose a technique of synthesizing an asynchronous pipeline controller in a way to share delay buffers among setup timing paths on pipeline stages for minimally allocating total delay buffers. In addition, we devise an area-efficient delay circuit structure called delay path unit (DPU) by extending the proposed delay path sharing concept and propose an in-depth synthesis flow of an asynchronous pipeline controller using DPUs. Through experiments with benchmark circuits using a 45-nm cell library, it is shown that our techniques of synthesizing asynchronous pipeline controllers are able to reduce the controller area by up to 46.3%-59.4% and the leakage power by up to 33.0%-49.0% on average while retaining the same level of performance.