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Simulink(R)-based heterogeneous multiprocessor SoC design flow for mixed Hardware/Software refinement and Simulation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Sang-Il | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.contributor.author | Brisolara, Lisane | - |
dc.contributor.author | Carro, Luigi | - |
dc.contributor.author | Popovici, Katalin | - |
dc.contributor.author | Guerin, Xavier | - |
dc.contributor.author | Jerraya, Ahmed A. | - |
dc.contributor.author | Huang, Kai | - |
dc.contributor.author | Li, Lei | - |
dc.contributor.author | Yan, Xiaolang | - |
dc.date.accessioned | 2009-12-17T02:24:38Z | - |
dc.date.available | 2009-12-17T02:24:38Z | - |
dc.date.issued | 2009 | - |
dc.identifier.citation | Integration, the VLSI Journal 42 pp.227-245 | en |
dc.identifier.issn | 0167-9260 | - |
dc.identifier.uri | https://hdl.handle.net/10371/21096 | - |
dc.description.abstract | As a solution for dealing with the design complexity of multiprocessor SoC architectures, we present a joint Simulink-SystemC design flow that enables mixed hardware/software refinement and simulation in the early design process. First, we introduce the Simulink combined algorithm/architecture model (CAAM) unifying the algorithm and the abstract target architecture. From the Simulink CAAM, a hardware architecture generator produces architecture models at three different abstract levels, enabling a trade-off between simulation time and accuracy. A multithread code generator produces memory-efficient multithreaded programs to be executed on the architecture models. To show the applicability of the proposed design flow, we present experimental results on two real video applications. | en |
dc.language.iso | en | - |
dc.publisher | Elsevier | en |
dc.subject | Application to architecture mapping | en |
dc.subject | Codesign | en |
dc.subject | Design space exploration | en |
dc.subject | Memory optimization | en |
dc.subject | Multiprocessor system-on-chip | en |
dc.subject | Simulation | en |
dc.subject | Simulink | en |
dc.subject | System specification | en |
dc.title | Simulink(R)-based heterogeneous multiprocessor SoC design flow for mixed Hardware/Software refinement and Simulation | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 한상일 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
dc.identifier.doi | 10.1016/j.vlsi.2008.08.003 | - |
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