Browse

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

Cited 0 time in Web of Science Cited 0 time in Scopus
Authors
Han, Sang-Il; Baghdadi, Amer; Bonaciu, Marius Petru; Chae, Soo-Ik; Jerraya, Ahmed Amine
Issue Date
2004-06
Citation
Design Automation Conference, pp.250-255
Keywords
Multiprocessor SoCMessage passingData transfer architectureMemory ServerNetwork on chipNetwork Interface
Abstract
Massive data transfer encountered in emerging multimedia
embedded applications requires architecture allowing both highly
distributed memory structure and multiprocessor computation to be
handled. The key issue that needs to be solved is then how to
manage data transfers between large numbers of distributed
memories. To overcome this issue, our paper proposes a scalable
Distributed Memory Server (DMS) for multiprocessor SoC
(MPSoC). The proposed DMS is composed of: (1) highperformance
and flexible memory service access points (MSAPs),
which execute data transfers without intervention of the processing
elements, (2) data network, and (3) control network. It can handle
direct massive data transfer between the distributed memories of
an MPSoC. The scalability and flexibility of the proposed DMS
are illustrated through the implementation of an MPEG4 video
encoder for QCIF and CIF formats. The experiments show clearly
how DMS can be adapted to accommodate different SoC
configurations requiring various data transfer bandwidths.
Synthesis results show that bandwidth can scale up to 28.8 GB/sec.
Language
English
URI
https://hdl.handle.net/10371/21445
Files in This Item:
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse