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아날로그 싱크로너스 미러 딜레이 기법을 이용한 고속 locking 특성을 갖는 동기시스템의 설계 : A Design of fast locking clock generator using analog synchronous mirror delay technique for high speed DRAM application
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 김원찬 | - |
dc.contributor.author | 심대윤 | - |
dc.date.accessioned | 2010-01-15T04:22:48Z | - |
dc.date.available | 2010-01-15T04:22:48Z | - |
dc.date.copyright | 2000. | - |
dc.date.issued | 2000 | - |
dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000069161 | kor |
dc.identifier.uri | https://hdl.handle.net/10371/30912 | - |
dc.description | 학위논문(박사)--서울대학교 대학원 :전기공학부,2000. | ko |
dc.format.extent | viii, 106 장 | ko |
dc.language.iso | ko | ko |
dc.publisher | 서울대학교 대학원 | ko |
dc.subject | 클럭 발생기 | ko |
dc.subject | clock cynchronization | ko |
dc.subject | synchronous mirror delay (SMD) | ko |
dc.subject | comparator | ko |
dc.subject | locking | ko |
dc.subject | fast locking | ko |
dc.subject | duty cycle corrector | ko |
dc.subject | static phase error | ko |
dc.title | 아날로그 싱크로너스 미러 딜레이 기법을 이용한 고속 locking 특성을 갖는 동기시스템의 설계 | ko |
dc.title.alternative | A Design of fast locking clock generator using analog synchronous mirror delay technique for high speed DRAM application | ko |
dc.type | Thesis | - |
dc.contributor.department | 전기공학부 | - |
dc.description.degree | Doctor | ko |
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