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A study on the low-noise high-speed sensing architectures for multi gigabit DRAMs : 기가 비트 DRAM을 위한 저잡음 고속센싱 방법에 관한 연구

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dc.contributor.advisor서광석-
dc.contributor.author김종식-
dc.date.accessioned2010-01-15T04:24:00Z-
dc.date.available2010-01-15T04:24:00Z-
dc.date.copyright1999.-
dc.date.issued1999-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000071876eng
dc.identifier.urihttps://hdl.handle.net/10371/30941-
dc.descriptionThesis (doctoral)--서울대학교 대학원 :전기공학부,1999.en
dc.format.extentvi, 129 p.en
dc.language.isoenen
dc.publisher서울대학교 대학원en
dc.subject비트 라인en
dc.subjectDynamic Random Access Memoryen
dc.subject센스 엠프en
dc.subjectBit line sense amplifieren
dc.subjectMemory 셀en
dc.subjectMemory cellen
dc.subject셀 노이즈en
dc.subjectCell array noiseen
dc.subjectMOSFETen
dc.titleA study on the low-noise high-speed sensing architectures for multi gigabit DRAMsen
dc.title.alternative기가 비트 DRAM을 위한 저잡음 고속센싱 방법에 관한 연구-
dc.typeThesis-
dc.contributor.department전기공학부-
dc.description.degreeDoctoren
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