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상위단계 합성에서의 타이밍 최적화를 위한 버퍼 삽입 활용 : Utilization of Buffer Insertion for Timing Optimization in High-level Synthesis
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- Authors
- Advisor
- 김태환
- Issue Date
- 2009
- Publisher
- 서울대학교 대학원
- Keywords
- 타이밍 ; Timing ; 상위 단계 합성 ; High-Level Synthesis ; 버퍼 삽입 ; buffer insertion ; 설계 흐름 ; Physical design ; design flow
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2009.8.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038751
https://hdl.handle.net/10371/44669
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