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Hardware Implementation of Min-Sum Decoder for Quasi-Cyclic Low-Density Parity Check (QC-LDPC) Codes : QC-LDPC 부호를 위한 Min-Sum 복호기의 구현

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Authors

Otgontsetseg Sukhbaatar

Advisor
성원용
Issue Date
2009
Publisher
서울대학교 대학원
Keywords
Low-density parity check (LDPC) codes ; min-sum (MS) algorithm ; quasi-cyclic (QC) codes
Description
Thesis(masters) --서울대학교 대학원 :전기. 컴퓨터공학부,2009.8.
Language
English
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038742

https://hdl.handle.net/10371/44677
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