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Power reduction in look-up table based FPGAs by glitch minimization
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 장래혁 | - |
| dc.contributor.author | 임현민 | - |
| dc.date.accessioned | 2010-02-04T23:20:43Z | - |
| dc.date.available | 2010-02-04T23:20:43Z | - |
| dc.date.copyright | 2005. | - |
| dc.date.issued | 2005 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000052883 | eng |
| dc.identifier.uri | https://hdl.handle.net/10371/50027 | - |
| dc.description | Thesis(master`s)--서울대학교 대학원 :전기.컴퓨터공학부,2005. | en |
| dc.format.extent | v, 37 leaves | en |
| dc.language.iso | en | en |
| dc.publisher | 서울대학교 대학원 | en |
| dc.subject | FPGA | en |
| dc.subject | 저전력 | en |
| dc.subject | power-reduction | en |
| dc.subject | 최적화 | en |
| dc.subject | optimization | en |
| dc.subject | NP-complete | en |
| dc.subject | NP-complete | en |
| dc.subject | 시뮬레이션 | en |
| dc.subject | simulation | en |
| dc.title | Power reduction in look-up table based FPGAs by glitch minimization | en |
| dc.type | Thesis | - |
| dc.contributor.department | 전기.컴퓨터공학부 | - |
| dc.description.degree | Master | en |
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