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Deep-submicron 반도체 공정에서 안정된 데이터 유지 전압을 지원하는 파워게이팅 구조 : (A)Power gating structure to stabilize data-retention voltage in deep-submicron CMOS technology

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dc.contributor.advisor김수환-
dc.contributor.author최창준-
dc.date.accessioned2010-02-09T14:56:03Z-
dc.date.available2010-02-09T14:56:03Z-
dc.date.copyright2007.-
dc.date.issued2007-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000045810kog
dc.identifier.urihttps://hdl.handle.net/10371/53513-
dc.description학위논문(석사)--서울대학교 대학원 :전기·컴퓨터공학부,2007.ko
dc.format.extentvii, 55 장ko
dc.language.isokoko
dc.publisher서울대학교 대학원ko
dc.subject파워게이팅ko
dc.subjectPower gatingko
dc.subject데이터 유지 전압ko
dc.subjectLow powerko
dc.subject슬립 트랜지스터ko
dc.subjectSleep Transistorko
dc.subject나노미터ko
dc.subjectLeakage currentko
dc.subject저전력ko
dc.subjectData-retention voltageko
dc.subject그라운드 바운스 노이즈.ko
dc.subjectGround-bounce noise.ko
dc.titleDeep-submicron 반도체 공정에서 안정된 데이터 유지 전압을 지원하는 파워게이팅 구조ko
dc.title.alternative(A)Power gating structure to stabilize data-retention voltage in deep-submicron CMOS technologyko
dc.typeThesis-
dc.contributor.department전기·컴퓨터공학부-
dc.description.degreeMasterko
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