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Implementation of an OpenVG Rasterizer with Configurable Anti-aliasing and Multi-window Scissoring
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Huang, Ren | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2010-04-01T01:01:21Z | - |
dc.date.available | 2010-04-01T01:01:21Z | - |
dc.date.issued | 2006-09 | - |
dc.identifier.citation | IEEE International Conference on Computer and Information Technology, pages 179-184 | en |
dc.identifier.uri | https://hdl.handle.net/10371/62265 | - |
dc.description.abstract | This paper describes an OpenVG-compliant hardware
rasterizer with configurable anti-aliasing and multi-window scissoring. This rasterizer requires 129K logic gates with 2KB on-chip SRAM and provides satisfactory image quality with a reasonable rasterizer speed at the operational frequency of 100MHz. In this paper, we propose an optimized scanline algorithm, which provides better performance than the conventional scanline algorithm with supersampline while maintaining the flexibility and the hardware simplicity. We also propose a fast LUT-based scissoring algorithm, which has zero-latency in most of the cases. The hardware implementation of this rasterizer is explained in detail. | en |
dc.language.iso | en | en |
dc.title | Implementation of an OpenVG Rasterizer with Configurable Anti-aliasing and Multi-window Scissoring | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 채수익 | - |
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