Browse

Fin and Recess Channel MOSFET for High Speed and Low Power DRAM Cell
고속 저전력 디램 셀을 위한 핀과 리세스 혼합 채널 MOSFET

DC Field Value Language
dc.contributor.advisor박병국-
dc.contributor.author송재영-
dc.date.accessioned2010-05-04T05:32:33Z-
dc.date.available2010-05-04T05:32:33Z-
dc.date.copyright2010-
dc.date.issued2010-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000032541eng
dc.identifier.urihttp://hdl.handle.net/10371/63984-
dc.descriptionThesis(doctors) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.en
dc.format.extentvi, 132 p.en
dc.language.isoenen
dc.publisher서울대학교 대학원en
dc.subject핀과 리세스 혼합 채널 MOSFET (FiReFET)en
dc.subjectFin and Recess Channel MOSFET (FiReFET)en
dc.subject함몰게이트 구조en
dc.subjectburied-gate structureen
dc.subject소스en
dc.subjectsourceen
dc.subject드레인 저항en
dc.subjectdrain resistanceen
dc.subject게이트 유도 드레인 누설 (GIDL)en
dc.subjectGate-Induced Drain Leakage (GIDL)en
dc.subject다이내믹 랜덤 액세스 메모리 (DRAM)en
dc.subjectDynamic Random Access Memory (DRAM)en
dc.subject고속en
dc.subjecthigh speeden
dc.subject저전력en
dc.subjectlow poweren
dc.titleFin and Recess Channel MOSFET for High Speed and Low Power DRAM Cellen
dc.title.alternative고속 저전력 디램 셀을 위한 핀과 리세스 혼합 채널 MOSFETen
dc.typeThesis-
dc.contributor.department전기. 컴퓨터공학부-
dc.description.degreeDoctoren
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
Files in This Item:
There are no files associated with this item.
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse