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지연시간 편차를 고려한 클락 버퍼 위상 지정 기법 : Clock Buffer Polarity Assignment Considering the Effect of Delay Variations

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dc.contributor.advisor김태환-
dc.contributor.author강민석-
dc.date.accessioned2010-05-10T09:57:25Z-
dc.date.available2010-05-10T09:57:25Z-
dc.date.copyright2010-
dc.date.issued2010-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033417kog
dc.identifier.urihttps://hdl.handle.net/10371/65223-
dc.description학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.ko
dc.format.extentiv, 28 장ko
dc.language.isokoko
dc.publisher서울대학교 대학원ko
dc.subject클락 트리ko
dc.subjectclock treeko
dc.subject시간 편차ko
dc.subjecttiming variationko
dc.subject전원 노이즈ko
dc.subjectpowerko
dc.subject회로 최적화ko
dc.subjectground noiseko
dc.subjectoptimization circuitsko
dc.title지연시간 편차를 고려한 클락 버퍼 위상 지정 기법ko
dc.title.alternativeClock Buffer Polarity Assignment Considering the Effect of Delay Variationsko
dc.typeThesis-
dc.contributor.department전기. 컴퓨터공학부-
dc.description.degreeMasterko
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