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재구성 가능 연산을 위한 메모리 중심 통신 아키텍처
Memory-centric Communication Architecture for Reconfigurable Computing

DC Field Value Language
dc.contributor.advisor최기영-
dc.contributor.author장경욱-
dc.date.accessioned2010-05-10T09:57:32Z-
dc.date.available2010-05-10T09:57:32Z-
dc.date.copyright2010-
dc.date.issued2010-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033415kog
dc.identifier.urihttps://hdl.handle.net/10371/65225-
dc.description학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.ko
dc.format.extentⅳ, 35 장ko
dc.language.isokoko
dc.publisher서울대학교 대학원ko
dc.subject메모리 중심 통신 아키텍처ko
dc.subjectMemory-Centricko
dc.subject재구성 가능 연산 구조ko
dc.subjectCGRAko
dc.subject재구성 가능 연산 모듈ko
dc.subjectReconfigurable Array Architectureko
dc.subjectCommunication Overheadko
dc.subjectCommunication Overheadko
dc.title재구성 가능 연산을 위한 메모리 중심 통신 아키텍처ko
dc.title.alternativeMemory-centric Communication Architecture for Reconfigurable Computingko
dc.typeThesis-
dc.contributor.department전기. 컴퓨터공학부-
dc.description.degreeMasterko
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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