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Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

DC Field Value Language
dc.contributor.authorKim, Suhwan-
dc.contributor.authorChoi, Chang Jun-
dc.contributor.authorJeong, Deog-Kyoon-
dc.contributor.authorStephen V., Kosonocky-
dc.contributor.authorPark, Sung Bae-
dc.date.accessioned2010-06-29T23:31:54Z-
dc.date.available2010-06-29T23:31:54Z-
dc.date.issued2008-01-
dc.identifier.citationIEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 197-205en
dc.identifier.issn0018-9383-
dc.identifier.urihttps://hdl.handle.net/10371/68009-
dc.description.abstractPower gating is one of the most effective techniques
in reducing leakage power, which increases exponentially with
device scaling. However, large ground bounces during abrupt
changes of power mode may cause unwanted transitions in neighboring
circuits, which should still be operating normally. We
analyzed this ground-bounce noise and reduced it with novel
power-gating structures that utilize holistic integrated devicecircuit-
architecture approaches. We control the amount of charge
in the intermediate nodes of the circuit that passes through the
sleep transistors during the wake-up transition and stabilize the
minimum virtual power supply voltage required for data retention.
These techniques have been proven in silicon using 65-nm
bulk CMOS technology.
en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectCMOS technology scalingen
dc.subjectdevice/circuiten
dc.subjectground-bounce noiseen
dc.subjectpower-gating techniqueen
dc.titleReducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structuresen
dc.typeArticleen
dc.contributor.AlternativeAuthor김수환-
dc.contributor.AlternativeAuthor최창준-
dc.contributor.AlternativeAuthor정덕균-
dc.contributor.AlternativeAuthor박성배-
dc.identifier.doi10.1109/TED.2007.911067-
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