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High-resolution time-to-digital converter utilising fractional difference conversion scheme

Cited 7 time in Web of Science Cited 9 time in Scopus
Authors
Xing, Nan; Shin, W.-Y.; Jeong, K.-K.; Kim, Suhwan
Issue Date
2010-03-18
Publisher
Institution of Engineering and Technology
Citation
Electronics Letters- IEE (2010),46(6):398
Keywords
digital converterHigh-resolution
Abstract
A high-resolution process, voltage and temperature (PVT)-insensitive
time-to-digital converter (TDC) is presented, based on a Vernier
delay-line, in which the propagation delays in the upper and lower
buffer chains are stabilised by two different delay-locked-loops
(DLLs). The limitation on its resolution, imposed by DLL jitter and
input range of time intervals, is analysed. Simulation results show
that the proposed TDC achieves a resolution as high as 22.7 ps while
consuming only 2.7 mW.
ISSN
0013-5194
Language
English
URI
https://hdl.handle.net/10371/68011
DOI
https://doi.org/10.1049/el.2010.2698
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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