High-resolution time-to-digital converter utilising fractional difference conversion scheme

Abstract

A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different delay-locked-loops (DLLs). The limitation on its resolution, imposed by DLL jitter and input range of time intervals, is analysed. Simulation results show that the proposed TDC achieves a resolution as high as 22.7 ps while consuming only 2.7 mW.