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A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider

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Authors
Kim, Deok-Soo; Song, Heesoo; Kim, Taeho; Kim, Suhwan; Jeong, Deog-Kyoon
Issue Date
2009-11
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Asian Solid-State Circuits Conference, November 16-18, 2009 / Taipei, Taiwan, pp. 161-164
Abstract
A 1.35GHz all-digital phase-locked loop (ADPLL)
with an adaptively controlled loop filter and a 1/3rd-resolution
fractional divider is presented. The adaptive loop gain controller
(ALGC) effectively reduces the nonlinear characteristics of the
bang-bang phase-frequency detector (BBPFD). The fractional
divider partially compensates for the input phase error which is
caused by the fractional-N frequency synthesis operation. A
prototype ADPLL using a BBPFD with a dead zone free retimer,
an ALGC, and a fractional divider is fabricated in 0.13􀈝m
CMOS. The core occupies 0.19mm2 and consumes 13.7mW from
a 1.2V supply. The measured RMS jitter was 4.17ps at a
1.35GHz clock output.
Language
English
URI
https://hdl.handle.net/10371/68016
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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