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Parallel Scalability in Speech Recognition

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dc.contributor.authorYou, Kisun-
dc.contributor.authorChong, Jike-
dc.contributor.authorYi, Youngmin-
dc.contributor.authorGonina, Ekaterina-
dc.contributor.authorChristopher.J., Hughes-
dc.contributor.authorChen, Yen-Kuang-
dc.contributor.authorSung, Wonyong-
dc.contributor.authorK., Keutzer-
dc.date.accessioned2010-07-23-
dc.date.available2010-07-23-
dc.date.issued2009-11-
dc.identifier.citationIEEE Signal Processing Magazine, vol. 25, no. 6, pp. 124-135en
dc.identifier.issn1053-5888-
dc.identifier.urihttps://hdl.handle.net/10371/68656-
dc.description.abstractWe propose four application-level implementation alternatives called algorithm styles and construct highly optimized implementations on two parallel platforms: an Intel Core i7 multicore processor and a NVIDIA GTX280 manycore processor. The highest performing algorithm style varies with the implementation platform. On a 44-min speech data set, we demonstrate substantial speedups of 3.4 X on Core i7 and 10.5 X on GTX280 compared to a highly optimized sequential implementation on Core i7 without sacrificing accuracy. The parallel implementations contain less than 2.5% sequential overhead, promising scalability and significant potential for further speedup on future platforms.en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleParallel Scalability in Speech Recognitionen
dc.typeArticleen
dc.contributor.AlternativeAuthor유기선-
dc.contributor.AlternativeAuthor이영민-
dc.contributor.AlternativeAuthor성원용-
dc.identifier.doi10.1109/MSP.2009.934124-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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