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A Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filter

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dc.contributor.authorShin, Woo-Yeol-
dc.contributor.authorKim, Manho-
dc.contributor.authorHong, Gi-Moon-
dc.contributor.authorKim, Suhwan-
dc.date.accessioned2010-11-08T22:27:34Z-
dc.date.available2010-11-08T22:27:34Z-
dc.date.issued2010-08-
dc.identifier.citationIEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1856-1859en
dc.identifier.issn0098-3063-
dc.identifier.urihttps://hdl.handle.net/10371/70061-
dc.description.abstractAbstract — We reduce the pattern jitter and acquisition
time of a phase-locked loop (PLL) by adopting the split halfduty
sampled feedforward loop filter. A prototype designed
and fabricated in a 0.18􀈝m standard CMOS technology has a
40% lower acquisition time than a PLL without operating in
fast acquisition mode. Its peak-to-peak jitter is 26% less than
that of a PLL with a conventional 2nd-order RC loop filter.
en
dc.description.sponsorshipThis work was supported by the IT R&D program of MKE/KEIT
[Development of Standard Technology for Next Generation Semiconductor
Devices and Equipments]
en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectAcquisition timeen
dc.subjectloop filteren
dc.subjectpattern jitteren
dc.subjectphase locked loop (PLL)en
dc.titleA Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filteren
dc.typeArticleen
dc.contributor.AlternativeAuthor신우열-
dc.contributor.AlternativeAuthor김만호-
dc.contributor.AlternativeAuthor홍기문-
dc.contributor.AlternativeAuthor김수환-
dc.identifier.doi10.1109/TCE.2010.5606337-
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