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A Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filter
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Woo-Yeol | - |
dc.contributor.author | Kim, Manho | - |
dc.contributor.author | Hong, Gi-Moon | - |
dc.contributor.author | Kim, Suhwan | - |
dc.date.accessioned | 2010-11-08T22:27:34Z | - |
dc.date.available | 2010-11-08T22:27:34Z | - |
dc.date.issued | 2010-08 | - |
dc.identifier.citation | IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1856-1859 | en |
dc.identifier.issn | 0098-3063 | - |
dc.identifier.uri | https://hdl.handle.net/10371/70061 | - |
dc.description.abstract | Abstract — We reduce the pattern jitter and acquisition
time of a phase-locked loop (PLL) by adopting the split halfduty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18m standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter. | en |
dc.description.sponsorship | This work was supported by the IT R&D program of MKE/KEIT
[Development of Standard Technology for Next Generation Semiconductor Devices and Equipments] | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Acquisition time | en |
dc.subject | loop filter | en |
dc.subject | pattern jitter | en |
dc.subject | phase locked loop (PLL) | en |
dc.title | A Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filter | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 신우열 | - |
dc.contributor.AlternativeAuthor | 김만호 | - |
dc.contributor.AlternativeAuthor | 홍기문 | - |
dc.contributor.AlternativeAuthor | 김수환 | - |
dc.identifier.doi | 10.1109/TCE.2010.5606337 | - |
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