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A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Deok-Soo | - |
dc.contributor.author | Song, Heesoo | - |
dc.contributor.author | Kim, Taeho | - |
dc.contributor.author | Kim, Suhwan | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2010-11-18T06:27:40Z | - |
dc.date.available | 2010-11-18T06:27:40Z | - |
dc.date.issued | 2010-11 | - |
dc.identifier.citation | IEEE Journal of Solid State Circuits, vol.45, no.11, pp. 2300-2311 | en |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/70167 | - |
dc.description.abstract | Abstract—A 0.3–1.4 GHz all-digital phase locked loop (ADPLL)
with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13- m CMOS logic process. The core occupies 0.2 mm and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Adaptive gain control | en |
dc.subject | all-digital phase locked loop (ADPLL) | en |
dc.subject | bang-bang phase and frequency detector (BBPFD) | en |
dc.subject | false position method | en |
dc.subject | fractional divider | en |
dc.subject | frequency search | en |
dc.title | A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김덕수 | - |
dc.contributor.AlternativeAuthor | 송희수 | - |
dc.contributor.AlternativeAuthor | 김태호 | - |
dc.contributor.AlternativeAuthor | 김수환 | - |
dc.contributor.AlternativeAuthor | 정덕균 | - |
dc.identifier.doi | 10.1109/JSSC.2010.2064050 | - |
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