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A 5-Gb/s Digitally Controlled 3-Tap DFE Receiver for Serial Communications

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Authors
Han, Jae-Duk; Shin, Woo-Yeol; Choi, Woo-Seok; Chun, Jung-Hoon; Kim, Suhwan; Jeong, Deog-Kyoon
Issue Date
2010-11
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Asian Solid-State Circuits Conference, November 8-10, 2010, Beijing, China
Abstract
Decision feedback equalizers (DFEs) play a critical
role in high-speed communications through band-limited
channels. We implemented a 3-tap DFE receiver for 5-Gb/s data
bandwidth. To realize a multi-tap DFE operation, a digitalcontrol
scheme is proposed that does not use analog circuits for
biasing, such as DACs. In addition to the conventional loop
unrolling, several techniques including combined feedback are
used to reduce the latency of the feedback path. Fabricated in a
0.13-μm CMOS process, the prototype of the proposed DFE core
has an area of 0.009 mm2 and consumes 8.4 mW from a 1.2-V
supply, achieving a BER of less than 10-11 over a pair of 28-inch
Nelco 4000-6 board traces.
Language
English
URI
https://hdl.handle.net/10371/70169
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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