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Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

Cited 4 time in Web of Science Cited 2 time in Scopus
Authors
Jhang, Kyoung-Son; Ha, Soonhoi; Jhon, Chu Shik
Issue Date
1998
Publisher
Hindawi Publishing Corporation
Citation
VLSI Design, vol. 7, no. 1, pp. 85-95, 1998
Keywords
VLSIcoupling capacitancecrosstalkchannel routingtrack permutationsegment rearrangement
Abstract
The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication
technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk
caused by the coupling capacitance between adjacent wires in the layout design for the
fast and safe VLSI circuits. We present a simulated annealing approach based on
segment rearrangement to crosstalk minimization in an initially gridded channel
routing. The proposed technique is compared with previous track-oriented techniques,
especially a track permutation technique whose performance is bounded by an
exhaustive track permutation algorithm. Experiments showed that the presented
technique is more effective than the track permutation technique.
ISSN
1065-514X
Language
English
URI
http://hdl.handle.net/10371/7407
DOI
https://doi.org/10.1155/1998/81296
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
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