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Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bhattacharyya, Shuvra S. | - |
dc.contributor.author | Buck, Joseph T. | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.contributor.author | Lee, Edward A. | - |
dc.date.accessioned | 2009-08-24T03:12:45Z | - |
dc.date.available | 2009-08-24T03:12:45Z | - |
dc.date.issued | 1995-03 | - |
dc.identifier.citation | IEEE Trans. Circ. Syst., vol. 42, pp. 138-150, Mar. 1995 | en |
dc.identifier.issn | 1057-7122 | - |
dc.identifier.uri | https://hdl.handle.net/10371/7553 | - |
dc.description.abstract | Synchronous dataflow (SDF) semantics are wellsuited to representing and compiling multirate signal processing algorithms. A key to this match is the ability to cleanly express iteration without overspecifying the execution order of computations, thereby allowing efficient schedules to be constructed. Due to limited program memory, it is often desirable to translate the iteration in an SDF graph into groups of repetitive Wring patterns so that loops can be constructed in the target code. This paper establishes fundamental topological relationships between iteration and looping in SDF graphs, and presents a scheduling framework that provably synthesizes the most compact looping structures for a large class of practical SDF graphs. By modularizing different components of the scheduling framework, and establishing their independence, we show how other scheduling objectives, such as minimizing data buffering requirements or increasing the number of data transfers that occur in registers, can be incorporated in a manner that does not conflict with the goal of code compactness. | en |
dc.description.sponsorship | This work was part of the Ptolemy project, supported by the Advanced Research Projects Agency and U. S. Air Force (RASSP program, Contract F33615-93-C-1317), Semiconductor Research Corporation (Project 94-DC-008), National Science Foundation (MIP-9201605), Office of Naval Technology (Naval Research Laboratories), State of California MICRO program, and the following companies: Bell Northern Research, Cadence, Dolby, Hitachi,Mentor Graphics, Mitsubishi, NEC, Pacific Bell, Philips, Rockwell, Sony, and Synopsys. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Signal processing | en |
dc.subject | Digital processing | en |
dc.subject | Data flow | en |
dc.subject | Synchronous | en |
dc.subject | Assembler | en |
dc.subject | Code generation | en |
dc.title | Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 하순회 | - |
dc.identifier.doi | 10.1109/81.376876 | - |
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