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Performance Analysis of LDPC Coded DMT Systems with Bit-loading Algorithms for Powerline Channel
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Seong-Cheol | - |
| dc.contributor.author | Kim, Kyong-Hoe | - |
| dc.date.accessioned | 2009-08-25T07:57:58Z | - |
| dc.date.available | 2009-08-25T07:57:58Z | - |
| dc.date.issued | 2007-03-26 | - |
| dc.identifier.citation | ISPLC '07. IEEE International Symposium on Power Line Communications and Its Applications, pp. 234-239, 2007 | en |
| dc.identifier.uri | https://hdl.handle.net/10371/7804 | - |
| dc.description.abstract | This paper deals with two different approaches to
overcome unfavorable channel characteristics and to obtain higher performance of PLC systems: Low Density Parity Check (LDPC) coding and bit-loading algorithms for Discrete Multitone (DMT) modulation. We analyze the performance of LDPC coded DMT systems with bit-loading algorithms in terms of bit-error rate and data rate. Simulations are performed with statistically modeled in-home PLC channel and noise. Several bit-loading scenarios and LDPC coding schemes are also considered. The performances of the proposed DMT systems with and without LDPC codes are analyzed for the broadband PLC system design. | en |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.subject | Bit-loading | en |
| dc.subject | DMT | en |
| dc.subject | LDPC | en |
| dc.subject | PLC | en |
| dc.title | Performance Analysis of LDPC Coded DMT Systems with Bit-loading Algorithms for Powerline Channel | en |
| dc.type | Conference Paper | en |
| dc.contributor.AlternativeAuthor | 김성철 | - |
| dc.contributor.AlternativeAuthor | 김경회 | - |
| dc.identifier.doi | 10.1109/ISPLC.2007.371129 | - |
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