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Relaxed Barrier Synchronization for the BSP Model of Computation on Message-passing Architectures
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Jin-Soo | - |
| dc.contributor.author | Ha, Soonhoi | - |
| dc.contributor.author | Jhon, Chu Shik | - |
| dc.date.accessioned | 2009-08-28T05:21:11Z | - |
| dc.date.available | 2009-08-28T05:21:11Z | - |
| dc.date.issued | 1998-06 | - |
| dc.identifier.citation | Information Processing Letters, Vol. 66, No. 5, pp. 247-253, 1998 | en |
| dc.identifier.issn | 0020-0190 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/7991 | - |
| dc.description.abstract | In this paper, we relax the barrier synchronization constraint in the BSP model for the efficient implementation on message-passing architectures. Direct implementation of the barrier synchronization does not allow any processor to proceed past the synchronization point until all processors reach that point. Instead, in our relaxed barrier synchronization, the synchronization occurs at the time of accessing non-local data only between the producer and the consumer processors, eliminating the exchange of global information. | en |
| dc.language.iso | en | - |
| dc.publisher | Elsevier | en |
| dc.subject | Bulk Synchronous Parallel (BSP) model | en |
| dc.subject | Barrier synchronization | en |
| dc.subject | Message-passing architectures | en |
| dc.subject | Parallel processing | en |
| dc.title | Relaxed Barrier Synchronization for the BSP Model of Computation on Message-passing Architectures | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 김진수 | - |
| dc.contributor.AlternativeAuthor | 하순회 | - |
| dc.contributor.AlternativeAuthor | 전주식 | - |
| dc.identifier.doi | 10.1016/S0020-0190(98)00061-1 | - |
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