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Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Cited 8 time in Web of Science Cited 12 time in Scopus
Issue Date
2007-12
Publisher
Springer Verlag
Citation
DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, Vol.11, No.4, pp.249-283
Keywords
multithreaded code generationmemory size reductionmultiprocessor SoCSimulink
Description
This manuscript has been extended with multithreaded code generation based on Buffer memory optimization for video codec application modeled in Simulink by Sang-Il Han, Ahmed A. Jerraya, et. al., which appeared in the Proceedings of the DAC 2006 and Functional modeling techniques for
efficient SW code generation of video codec application by Sang-Il Han, Ahmed A. Jerraya, et. al., which appeared in the Proceedings of the ASPDAC 2006.
Abstract
Emerging embedded systems require heterogeneous multiprocessor SoC architectures that can satisfy both high-performance and programmability. However, as the complexity of embedded systems increases, software programming on an increasing number of multiprocessors faces several critical problems, such as multithreaded code generation, heterogeneous architecture adaptation, short design time, and low cost implementation. In this paper, we present a software code generation flow based on Simulink to address these problems. We propose a functional modeling style to capture data-intensive and control-dependent target applications, and a system architecture modeling style to seamlessly transform the functional model into the target architecture. Both models are described using Simulink. From a system architecture Simulink model, a code generator produces a multithreaded code, inserting thread and communication primitives to abstract the heterogeneity of the target architecture. In addition, the multithread code generator called LESCEA applies the extensions of dataflow based memory optimization techniques, considering both data and control dependency. Experimental results on a Motion-JPEG decoder and an H.264 decoder show that the proposed multithread code generator enables easy software programming on different multiprocessor architectures with substantially reduced data memory size (up to 68.0%) and code memory size (up to 15.9%).
ISSN
0929-5585
Language
English
URI
https://hdl.handle.net/10371/81016
DOI
https://doi.org/10.1007/s10617-007-9009-4
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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