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Exploring On-Chip Bus Architectures for Multitask Applications
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- Authors
- Issue Date
- 2004-12
- Citation
- Journal of Semiconductor Technology and Science (JSTS), Vol. 4 No.4, pp. 286-292, 2004
- Keywords
- Performance estimation ; multitask application ; on-chip bus ; design space exploration ; queuing theory
- Abstract
- In this paper we present a static
performance estimation technique of on-chip bus
architectures. The proposed technique requires the
static scheduling of function blocks of a task to
analyze bus conflicts caused by simultaneous
accesses from processing elements to which function
blocks are mapped. To apply it to multitask
applications, the concurrent execution of the
function blocks of different tasks also should be
considered. Since tasks are scheduled independently,
considering all cases of concurrency in each
processing element is impractical. Therefore we make
an average estimate on the effects of other tasks with
respect to bus request rate and bus access time. The
proposed technique was incorporated with our
exploration framework for on-chip bus architectures.
Its viability and efficiency are validated by a
preliminary example.
- ISSN
- 1598-1657
http://uci.or.kr/G300-j15981657.v4n4p286
- Language
- English
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