CMOS compatibility of a micromachining process developed for semiconductor neural probe

Abstract

Neural probes are made on silicon substrate using a micromachining process with low temperature steps only. A deep silicon etch ("Bosch") process was used for the probe shaping. CMOS compatibility of the process was checked and reported in this paper. Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step, while changes of test transistor characteristics were monitored. Threshold voltage was found virtually unchanged for both nand p-type MOS transistors. When excess plasma exposure was done, however, non-trivial shift in p-MOS threshold was observed.