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Showing results 1 to 7 of 7

Issue Date	Title / Author(s) / Citation	File
2009	Design of fully integrated CMOS 40-Gbs serial link transceiver 김정겸	link
2009	(A) study on the design of wide range CDR without a external reference clock 황문상	link
2018-04	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.4, pp.1192-1202	DOI
2019-08	Design of Wide-Range Clock and Data Recovery with Multi-Phase Oversampling Frequency Detection 박관서	view file link
2022-09	An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector Park, Suneui; Choi, Seojin; Yoo, Seyeon; Cho, Yoonseo; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2829-2840	DOI
2023	Design Techniques for Clock Generation and Recovery in Serial Interface 정우송	view file link
2023	A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth Bang, Jooeun; Jung, Seohee; Kim, Jaeho; Park, Suneui; Choi, Jaehyouk IEEE Solid-State Circuits Letters, Vol.6, pp.201-204	DOI