High Density 3-D Stacked NAND flash Memory Structure and Trap Characterization

Abstract

A new 3-D stacked NAND flash memory with the cell area of 3F2/n was proposed to achieve high-density NAND flash memory device by using common gate structure. By adopting trench structure instead of through-hole structure, threshold voltage variation in cells of a string can be reduced and the number of stacked control-gate electrodes in a gate stack can be increased as a result. In the trench between adjacent control gate stacks, gate stack, which consists of tunneling oxide/nitride storage layer/blocking oxide stack, poly-Si bodies, backside oxide (BOX). We showed that proposed device had the advantages of better reliability, cheaper process cost and lower variation of the threshold voltage and program speed than the 3-D stacked NAND flash memory cells in via-hole. To investigate the characteristics of proposed 3-D stacked NAND flash memory device, TCAD simulation tool was used. Firstly, we studied about body coupling effect with the bit-line voltage (VBL) and the geometry of the device. To solve the body coupling effect, we showed the guideline of circuit operation. We investigated the scaling down limitation of gate length and space, and optimized the geometry of proposed device. The modified contact scheme that connects both sides channels in bottom region was proposed. To overcome body cross-talk effect, we suggested the 3-D stacked NAND flash memory with shield layer. The 3-D stacked NAND flash memory device with shield layer has almost same structure. The effect of shield layer with shield type and shield bias was investigated by TCAD simulation. To implement the full array, we suggested the metal wiring of 3-D stacked NAND flash memory with shield layer for read and program operation. To confirm device characteristics, we fabricated proposed 3-D stacked NAND flash memory cell strings which have 3 layers of vertically stacked CGs. Vth could be controlled by applying a bias to the shield layer. We also showed reasonable cycling and retention characteristics of a cell in a string and good pass-gate properties of the cell in the bottom of the trench. In appendix section, Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated the effects of program/erase cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.