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Design Methodology for Mesh based Clock Networks
메쉬 기반의 클락 네트워크 설계 방법론

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dc.contributor.advisor김태환-
dc.contributor.author강민석-
dc.date.accessioned2017-07-13T07:07:35Z-
dc.date.available2017-07-13T07:07:35Z-
dc.date.issued2015-02-
dc.identifier.other000000025119-
dc.identifier.urihttp://hdl.handle.net/10371/119060-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 김태환.-
dc.description.abstractThe clock distribution network in a synchronous digital circuit delivers a clock signal to every storage element i.e., clock sink in the circuit. However, since the continued technology scaling increases PVT (process-voltage-temperature) variation, the increase of clock skew variation is highly likely to cause performance degradation or system failure at run time. Recently, to mitigate the clock skew variation, many researchers have taken a profound interest in the clock mesh network. However, though the structure of clock mesh network is excellent in tolerating timing variation, it demands significantly high power consumption due to the use of excessive mesh wire and buffer resources. Thus, optimizing the resources required in the mesh clock synthesis while maintaining the variation tolerance is crucially important. The three major tasks that greatly affect the cost of resulting clock mesh are (1) mesh segment allocation, (2) mesh buffer allocation and sizing, and (3) clock sink binding to mesh segments. Previous clock mesh optimization approaches solve the three tasks sequentially, one by one at a time, to manage the run time complexity of the tasks at the expense of losing the quality of results. However, since the three tasks are tightly inter-related, simultaneously optimizing all three tasks is essential, if the run time is ever permitted, to synthesize an economical clock mesh network. In this dissertation, we propose an approach which is able to tackle the problem in an integrated fashion by combining the three tasks into an iterative framework of incremental updates and solving them simultaneously to find a globally optimal allocation of mesh resources while taking into account the clock skew tolerance constraints. The core parts of this dissertation are a precise analysis on the relation among the resource optimization tasks and an establishment of mechanism for effective and efficient integration of the tasks. In particular, to handle the run time problem, we propose a set of speed-up techniques i.e., modeling RC circuit for eliminating redundant matrix multiplications, exploiting sliding window scheme, and fast buffer sizing effect estimation, which are fitted into our context of fast clock skew estimation in mesh resource optimization as well as an invention of early decision policies. In summary, this dissertation presents the efficient design methodology for clock mesh synthesis with consideration on integration of three tasks and reduction of runtime complexity.-
dc.description.tableofcontentsAbstract i
Contents iii
List of Figures vi
List of Tables x
1 Introduction 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . 3
2 Background 5
2.1 Clock Distribution Network . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Clock Network Topologies . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Design Metrics of Clock Network . . . . . . . . . . . . . . . . . . . 7
2.4 The Effects of Variations on Clock Skew . . . . . . . . . . . . . . . . 9
3 Clock Mesh Synthesis Flow 12
3.1 Elements of Clock Mesh . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Conventional Clock Mesh Synthesis Overview . . . . . . . . . . . . . 13
3.3 Initial Grid Generation . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Mesh Buffer Placement and Sizing . . . . . . . . . . . . . . . . . . . 14
3.5 Clock Mesh Optimization . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Integrated Resource Allocation and Binding in Clock Mesh Synthesis 19
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Framework of Clock Mesh Optimization . . . . . . . . . . . . . . . . 26
4.3.1 Incremental Resource Updates . . . . . . . . . . . . . . . . . 29
4.3.2 Constraints for Variation Tolerance . . . . . . . . . . . . . . 34
4.3.3 Early Decision Policies . . . . . . . . . . . . . . . . . . . . . 38
4.3.4 Time Complexity Analysis . . . . . . . . . . . . . . . . . . . 39
4.4 Fast Clock Skew Estimation Techniques . . . . . . . . . . . . . . . . 40
4.4.1 Partially Reusing Matrix Multiplication for Incremental Updates 41
4.4.2 Adopting Sliding Window Scheme . . . . . . . . . . . . . . . 43
4.4.3 Adjusting Delay Caused by Buffer Resizing . . . . . . . . . . 44
4.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5.1 Experimental Environments . . . . . . . . . . . . . . . . . . 46
4.5.2 Resource Requirement and Variation Tolerance Comparison . 48
4.5.3 Comparison with Clock Mesh Optimization using Worst Case Timing Analysis of Commercial Tool . . . . . . . . . . . . . 56
4.5.4 Analysis of the Effect of Proposed Techniques . . . . . . . . 58
4.5.5 Run Time Analysis . . . . . . . . . . . . . . . . . . . . . . . 61
4.5.6 Accuracy and Run Time of Fast Clock Skew Estimation . . . 63
4.5.7 Electromigration Analysis . . . . . . . . . . . . . . . . . . . 68
4.5.8 Run-time Analysis in Multi-thread Computing Environment . 70
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5 Conclusion 74
Abstract in Korean 84
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dc.formatapplication/pdf-
dc.format.extent1836877 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectVLSI & CAD-
dc.subjectclock mesh synthesis-
dc.subjectvariation tolerance-
dc.subjectresource allocation & binding-
dc.subject.ddc621-
dc.titleDesign Methodology for Mesh based Clock Networks-
dc.title.alternative메쉬 기반의 클락 네트워크 설계 방법론-
dc.typeThesis-
dc.contributor.AlternativeAuthorMinseok Kang-
dc.description.degreeDoctor-
dc.citation.pagesx, 84-
dc.contributor.affiliation공과대학 전기·컴퓨터공학부-
dc.date.awarded2015-02-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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