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Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 박병국 | - |
dc.contributor.author | 서주연 | - |
dc.date.accessioned | 2017-07-13T07:14:41Z | - |
dc.date.available | 2017-07-13T07:14:41Z | - |
dc.date.issued | 2016-02 | - |
dc.identifier.other | 000000133075 | - |
dc.identifier.uri | https://hdl.handle.net/10371/119179 | - |
dc.description | 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 박병국. | - |
dc.description.abstract | Exploding demands for mobile devices induce the drastic expansion of the market of NAND flash memory as high density storage devices. Three-dimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension. For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) is a roadblock in scaling-down of the minimum feature size, because channel diameter can be scaled down to < 20 nm. However, it is challenging to reduce the thickness of oxide-nitride-oxide (ONO) layer, since the charge trapping properties degrade when the Si3N4 is made thinner.
.In this thesis, the channel stacked NAND flash memory array (CSTAR) with high-κ charge trapping layer for high scalability is proposed. To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices. Finally, 4-layer channel stacked memory with high-κ layer was successfully fabricated and characterized. Recent trend of nonvolatile memories are introduced and the overview of 3D stacked NAND flash memory technology is presented in Chapter 1 and 2. In Chapter 3, the memory characteristics of high-κ layer were evaluated with fabricated capacitors and flash memory devices. In Chapter 4, fabrication process and electrical characteristics of CSTAR with high-κ are shown. With the comparison with previous works using ONO layer, CSTAR with high-κ is evaluated. In Chapter 5, the novel operation method of CSTAR is presented. Using TCAD and measurement, a newly designed operation method is verified | - |
dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Flash Memory Technology 1 1.2 Flash Memory Unit Cell and Array Structure 6 1.3 NAND Cell Operation 13 1.4 Charge Trap Flash Memory 25 Chapter 2 3-D Stacked NAND Flash Memory 28 2.2 Examination of Previous 3-D Stacked NAND Flash 28 2.2.1 Gate Stack Type 3-D NAND Flash Memory 28 2.2.2 Channel Stack Type 3-D NAND Flash Memory 36 2.2.3 Comparison between the Gate Stack Type and the Channel Stack Type 45 Chapter 3 Channel Stacked NAND Flash Memory with high- Charge Trapping Layer 48 3.1 Introduction 48 3.2 Memory Characteristics of HfO2 52 3.3 Fabrication of Nanowire Memory Devices with high-κ Dielectric Layer 56 Chapter 4 Fabrication of Channel Stacked NAND Flash Memory with High-κ 66 4.1 Introduction 66 4.2 Fabrication Method 67 4.3 Key Process Steps of CSTAR with high-κ 72 4.3.1 Single Crystalline Silicon Channel 72 4.3.2 Fin Patterning 74 4.3.3 Stacked Nanowires 76 4.4 Measurement Results 81 4.5 Comparison with Previous Works 88 Chapter 5 Novel Program Operation in CSTAR 92 5.1 Introduction. 92 5.2 Simulation Results 93 5.3 Measurement Results 103 Chapter 6 Conclusions 106 Bibliography 108 Abstract in Korean 116 List of Publications 118 | - |
dc.format | application/pdf | - |
dc.format.extent | 4487355 bytes | - |
dc.format.medium | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject | 3-D NAND flash memory | - |
dc.subject | stacked array (STAR) | - |
dc.subject | charge trap flash (CTF) | - |
dc.subject | high-κ charge trap memory | - |
dc.subject.ddc | 621 | - |
dc.title | Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability | - |
dc.type | Thesis | - |
dc.description.degree | Doctor | - |
dc.citation.pages | 135 | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2016-02 | - |
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