Implementation of Synaptic Plasticity and Learning functions using Si-Based Charge-Trap Memory

Abstract

The development of an energy efficient and highly integrated electronic synapse is an important step in the effort to mimic the adaptive learning and memory in a biological neural network. Recently, several types of two-terminal memristors have been proposed to emulate biologically inspired synaptic functions using various components such as atomic switches, phase-change memory (PCM), and resistive switching devices. However, these two terminal devices require one select device per cell in a cell array to imitate a synapse-neuron network. Moreover, they need to be improved in terms of reliability, repeatability and processing complexity. In this thesis, we propose a new silicon-based charge trap memory device with an Al2O3/HfO2/Si3N4 (A/H/N) gate stack to realize the imitation of memory features in a biological synapse. In a fabricated capacitor having the proposed gate stack, short-term plasticity (STP) and long-term potentiation (LTP) properties with their transition are demonstrated, which are similar to the behavior of biological synapses. A single charge trapping layer (Si3N4) on silicon interface induces fast charge loss by trap-assisted tunneling (TAT) or direct tunneling. In addition, there is no remarkable pulse interval dependence when repeated input pulses are applied, in which the pulse amplitude and width are same. However, more frequent input pulses leads to larger current changes with longer retention property when HfO2 layer is inserted on Si3N4 layer as a second charge trapping layer. It is originated from the deep trap level (ET) in HfO2 layer leading to a transition into long-term memory. Lastly, we proposed a pair of pre- and post-synaptic spike scheme for the synaptic device and STDP property was demonstrated from experimental data. This suggested architecture has remarkable advantages, including high uniformity over a large area, excellent reliability, the use of CMOS-compatible materials, and easy integration with CMOS circuits.