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Silicon-Based Synaptic Transistor for Neuromorphic Computing Systems : 신경계 모방 시스템을 위한 실리콘 기반 시냅스 모방 트랜지스터
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 박병국 | - |
dc.contributor.author | Hyungjin Kim | - |
dc.date.accessioned | 2017-07-13T07:21:30Z | - |
dc.date.available | 2017-07-13T07:21:30Z | - |
dc.date.issued | 2017-02 | - |
dc.identifier.other | 000000142151 | - |
dc.identifier.uri | https://hdl.handle.net/10371/119287 | - |
dc.description | 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 박병국. | - |
dc.description.abstract | Current computing systems based on the von Neumann architecture suffer from the fact that serious leakage current issues have risen up in nanoscale devices. Neuromorphic computing system has been believed to solve fundamental challenges in current computing system by mimicking a biological nervous system, especially in terms of parallel signal processing. Synaptic devices are considered as the one of the most important parts of neuromorphic systems because a biological synapse is thought to control signal transmissions and memory effects in our nervous system. However, the memristor, one of the strongest candidates for an artificial synapse, requires additional switching parts in order to transfer and receive signals using the same electrode, leading to extra overheads that may compromise the advantages of massive parallelism inherent in neuromorphic systems.
In this dissertation, a silicon-based synaptic transistor with asymmetric dual-gate structure is investigated. The structural feature enables the synaptic transistors to interact with both pre- and post-synaptic neuron circuits directly. A TCAD device simulator and a circuit simulator are used to verify its synaptic learning properties and study its mechanism fundamentally. After verifying all the fabrication flow using a process simulator, the synaptic transistors are fabricated through process techniques including two-step CMP processes. The electrical and synaptic characteristics of the fabricated devices are measured with a semiconductor parameter analyzer, and a device model is created based on the measured data. Furthermore, spiking neural network composed of them is verified systematically using the device model. From the simulation study and electrical measurement, synaptic learning rules are observed in the synaptic transistors including the transition from short-term to long-term memory and spike-timing dependent plasticity. In addition, the spiking neural network composed of the synaptic transistors boasted its ability of pattern recognition using MNIST data set. The total recognition accuracy of the hardware-based neural network system having 784 input nodes and 10 output nodes is improved to nearly 70% by adding inhibitory synapses. These results indicate that the synaptic transistor studied in this dissertation can be used as a synaptic device in neuromorphic systems thanks to its direct connectability with neuron circuits and synaptic learning properties. | - |
dc.description.tableofcontents | Chapter 1. Introduction 1
1.1. Fundamental Challenges in Current Computing System 1 1.2. Neurobiological Background 4 1.2.1. Synaptic Transmission 4 1.2.2. Short-Tem and Long-Term Memory 7 1.2.3. Spike-Timing Dependent Plasiticity 9 1.3. Neuromorphic Computing 12 1.4. Outline of the Dissertation 17 Chapter 2. Silicon-Based Synaptic Transistor 18 2.1. Device Configuration 18 2.2. Device Simulation Study 20 2.2.1. Transition from Short-Term to Long-Term Memory 21 2.2.2. Spike-Timing Dependent Plasticity Characteristics 28 2.3. Circuit Simulation Study 30 Chapter 3. Device Fabrication 34 3.1. Process Design and Fabrication Flow 34 3.2. Experimental Results 41 3.2.1. Deposition of Hard Mask and Patterning 41 3.2.2. Formation of G1 through CMP 44 3.2.3. Removal of Hard Mask 46 3.2.4. Fin Channel Formation Using Sidewall Spacer 48 3.2.5. Gate Splitting through CMP and Etchback Processes 50 Chapter 4. Device Characteristics 52 4.1. Field-Effect Transistor Characteristics 52 4.2. Synaptic Learning Properties 54 4.2.1. Transition from Short-Term to Long-Term Memory 54 4.2.2. Spike-Timing Dependent Plasticity Characteristics 58 Chapter 5. System Level Simulation 64 5.1. Hardware-Based Spiking Neural Network 64 5.2. Transferred Synaptic Weights from ANN Using ReLU 69 5.3. Addition of Inhibitory Synapse Part 73 Chapter 6. Conclusion 78 6.1. Review of Overall Work 78 6.2. Future Work 80 Appendix A. Multi-Threshold Voltages in Ultra Thin Body Devices by Asymmetric Dual-Gate Structure 82 Appendix B. Asymmetric Dual-Gate-Structured 1-T DRAM Cell for Retention Characteristics Improvement 90 Appendix C. A Single Memory Cell with Voltaile and Non-Volatile Memory Functions 101 Bibliography 109 Abstract in Korean 133 | - |
dc.format | application/pdf | - |
dc.format.extent | 4063789 bytes | - |
dc.format.medium | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject | asymmetric dual-gate structure | - |
dc.subject | neuromorphic system | - |
dc.subject | pattern recognition | - |
dc.subject | silicon-based synaptic transistor | - |
dc.subject | spiking neural network | - |
dc.subject | synaptic learning | - |
dc.subject.ddc | 621 | - |
dc.title | Silicon-Based Synaptic Transistor for Neuromorphic Computing Systems | - |
dc.title.alternative | 신경계 모방 시스템을 위한 실리콘 기반 시냅스 모방 트랜지스터 | - |
dc.type | Thesis | - |
dc.contributor.AlternativeAuthor | 김형진 | - |
dc.description.degree | Doctor | - |
dc.citation.pages | xi, 146 | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2017-02 | - |
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