DESIGN METHODOLOGY OF CONTINUOUS TIME ΔΣ MODULATOR FOR WIRELESS COMMUNICATION

Abstract

This thesis proposed the design methodology of continuous-time ΔΣ modulator for wireless application, and was implemented the proposed architecture as a chip in standard CMOS technology. Wireless application ADC should achieves high dynamic range, low power consumption and minimum active area. The continuous-time ΔΣ modulator (CTDSM) is an adequate candidate to satisfy those conditions at the same time, and it is robust to process variation on wafer. High dynamic range ADC relaxes the requirement of bandpass-filter and mixer. Most wireless application power is supplied by the battery power, low power consumption in ADC offers the opportunity to sustain a long system time and reduce the battery size. To design the CTDSM in circuit level is very time-consuming work. It is an alternative approach to use the MATLAB behavioral modeling, which is based on mathematical analysis, for speeding up the simulation time. This thesis enhanced the top-down design methodology, based on mathematical analysis, from high-level design to circuit level design. This method found out the problems from existed methodology and suggested the alternative design procedure. Behavioral modeling based on mathematical analysis offered the estimation of nonlinearity effect from circuit implementation. Through this methodology, we fabricated the prototype chip and measured the performance and operation of chip. Prototype modulator operates at 128MHz sampling frequency and it achieved 76.79dB of peak SNR, 70.31dB of peak SNDR and 72.3dB of SFDR at -3dBFS, 300kHz input tone. This results is averaged with 15-times of 2^16 point FFT data points. Checking the 15 FFT results without averaging, there is no exceptional case, which achieves over the mean peak SNDR within 1dB variation. We also observe the measured SNDR/SNR performance tendency by clock jitter variation. By comparing the measurement result against the post-layout simulation results. There is no difference in SNR performance. We assume that our analysis about designing CTDSM is quiet estimated by noise distribution and plan of analog specification. The total power consumption of CTDSM is 4.55mW at 128MHz sampling clock frequency. Auto tuning circuit consumes 820uW and it takes 1.4uS to calibrate the coefficients. Analog blocks consume 70% of total power and digital blocks consume 30% of total power. The chip is designed in 65nm CMOS and it has an active area of 600um x 800um.