A Modeling Methodology for Verification of High-Voltage Wordline Generator in NAND Flash Memory

Abstract

Conventionally, high-voltage wordline generator (HVWG) in NAND flash memory are verified using full-scale device-level models. When verifying operations of HVWG, the full-scale device-level models are accurate, but long simulation runtime is required. The key to fast verification is simple yet accurate models to reduce computation loads without sacrificing accuracy. This thesis proposes a modeling method to verify HVWG operations in NAND flash memory accurately. The proposed HVWG model includes input-output behaviors and power loss. HVWG generates high-voltages to program, erase, and read NAND flash memory. Since the HVWG drives wordlines of NAND flash memory, which corresponds to capacitive loads, output current should be modeled in order to correctly verify the system over various load conditions. Furthermore, power loss are also modeled to estimate power efficiency and input current consumption. While a modeling method for the HVWG is proposed in a previously reported literature, the output current cannot be accurately modeled. In this thesis, input-output behaviors of the circuits in the HVWG are modeled considering output current, and a power loss modeling method is proposed. The operations of the HVWG in NAND flash memory are verified with the models. The operations include generating high-voltages for programming and erasing memory cells and unselected wordlines and charging the wordlines. The full-scale device-level models are simulated using FineSim, which is a FastSPICE, and the models are simulated using XMODEL and compared with the full-scale device-level model simulation results. The model simulation results have errors less than 3% while simulation runtime is reduced by a factor of 5.88.